// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other 
// applicable license agreement, including, without limitation, 
// that your use is for the sole purpose of programming logic 
// devices manufactured by Altera and sold by Altera or its 
// authorized distributors.  Please refer to the applicable 
// agreement for further details.


// 
// Device: Altera EP4CE22F17C6 Package FBGA256
// 

//
// This file contains Fast Corner delays for the design using part EP4CE22F17C6,
// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
//

// 
// This SDF file should be used for ModelSim-Altera (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "DE0_NANO")
  (DATE "08/15/2018 18:19:04")
  (VENDOR "Altera")
  (PROGRAM "Quartus II 64-Bit")
  (VERSION "Version 15.0.0 Build 145 04/22/2015 Patches 0.01we SJ Web Edition")
  (DIVIDER .)
  (TIMESCALE 1 ps)

	// No Timing Cells with timing info are found in the compiled design. A dummy �dff� Timing Cell is created.
  (CELL
    (CELLTYPE "dff")
    (INSTANCE * )
  )
	// No Timing Cells with timing info are found in the compiled design. A dummy �dff� Timing Cell is created.
  (CELL
    (CELLTYPE "dff")
    (INSTANCE * )
  )
)
